1. Field of the Invention
The present invention relates to a frequency divider. More particularly, the present invention relates to a frequency divider with inner feedback.
2. Description of Related Art
With booming development of computer systems, system-on-chip (SoC) is also developed and widely used, which leads to a result that most of the present circuit designs trend to be digital systems. In a wireless communication SoC, design of a wireless transceiver thereof also trends to be an all-digital design. It is an important function for the transceiver to generate an oscillation source signal, and a circuit providing such function is naturally desired to be integrated with the digital circuit. A frequency synthesizer generally has the function of generating the oscillation source signal. Within such design field, an all digital phase-locked loop (ADPLL) has become one of the most important developing trends in recent documents. Since the digital circuit has a poor frequency-dividing performance under high frequency, the phase-locked loop (PLL) is generally implemented via an analog circuit, so as to achieve a better performance. Therefore, how to implement the analog PLL with the digital circuit and achieve an equivalent performance is an important subject for future researching.
Generally, a frequency divider is applied to the frequency synthesizer, a multimode frequency divider and a clock generator, etc. FIG. 1A is a system block diagram illustrating a conventional frequency synthesizer. Referring to FIG. 1A, the frequency synthesizer can also be referred to as the PLL. A phase-frequency detector (PFD) 101 compares a phase difference between a reference frequency Fref and a divided frequency of the radio frequency (RF) signal Rfout. A charge pump (CP) 102, a low-pass filter (LPF) 103 and a voltage-controlled oscillator (VCO) 104 generate a frequency of the RF signal Rfout according to the phase difference. Then, the output RF signal Rfout is fed back to the PFD 101 via a frequency divider 105 to determine whether phases of the input reference frequency Fref and the RF signal Rfout are the same. By such means, phases of the input reference frequency Fref and the RF signal Rfout can be adjusted to be the same, so as to achieve a phase-locked function.
FIG. 1B is a system block diagram illustrating a conventional multimode frequency divider. Referring to FIG. 1B, the frequency divider 105 is also referred to as a prescaler. The frequency divider 105 receives a high frequency signal RFin generated by an oscillator, and generates a frequency-divided frequency to a counter 106 according to a counting result of a counter 107. The counter 106 counts the frequency-divided frequency to generate a plurality of output signals Fm with different frequencies.
FIG. 1C is a system block diagram illustrating a conventional clock generator. Referring to FIG. 1C, a PLL 108 receives the reference frequency Fref to generate a frequency signal for the frequency divider 105, wherein the PLL 108 can be implemented via the circuit of FIG. 1A. Next, after frequency dividing performed by the frequency divider 105, a clock signal FCLK with a relatively low frequency is generated.
Circuits of all of the above applications include the frequency divider 105, while the frequency divider 105 can be implemented via a circuit of FIG. 1D. FIG. 1D is a system block diagram illustrating a conventional frequency divider. Referring to FIG. 1D, the frequency divider 105 is disclosed in a U.S. Pat. No. 7,012,985, in which the frequency divider 105 includes a first stage 110, a control delay circuit 112, a phase selector 114 and a dividing circuit 116. The first stage receives a non-inverting clock CLK—P and an inverting clock CLK—N, and outputs different phase signals with phase differences of 90° after operation. The control delay circuit 112 and the phase selector 114 coordinate with each other to select the different phase signals as clock signals for the dividing circuit 116. Finally, the dividing circuit 116 performs the dividing operation to output a clock signal CLKOUT.